FIG. 1 illustrates an interface of a chip 2 that incorporates a memory controller, to an external synchronous pipelined SRAM 4. An internal clock generated by the chip 2 is supplied to a clock output pad 6 that produces a SRAM clock sent to the SRAM 4 as a reference clock for supporting an interface to the SRAM 4.
As illustrated in FIG. 2, the SRAM clock driven by the chip 2 is always delayed with respect to the internal clock due to delays introduced by the clock pad 6 and the associated circuitry. Read time allocated for reading data from the SRAM 4 to the reading circuitry of the chip 2 is defined by a period between the leading or rising edge of the SRAM clock and the leading or rising edge of the next internal clock. Thus, as a result of the delay of the SRAM clock with respect to the internal clock, the read time becomes less than the internal clock cycle T. This problem is aggravated when the memory controller is running at higher frequencies.
Accordingly, it would be desirable to provide a clocking mechanism that would allow the read time to be increased.